1. Field of the Invention
This invention relates generally to a communications system and, more particularly, to a synchronization burst processor for use in a processing satellite of a satellite based cellular communications system.
2. Discussion of the Related Art
In a satellite based cellular communications system, a central terrestrial control processor or a network control center (NCC) generally controls one or more processing satellites operating within the communications system. Each processing satellite within the communications system services multiple users located in multiple geographic areas, known as ground cells. The processing satellites receive and transmit data signals to and from the multiple users or terrestrial terminals positioned at different locations within the ground cells on a point-to-point manner, via uplinks and downlinks. In a processing satellite using time division multiple access (TDMA) on the uplink from the terrestrial terminal to the processing satellite, it is necessary to provide a means of measuring the time of arrival of transmissions from the various terrestrial terminals in a given uplink beam so that the timing of the user transmissions may be adjusted to maintain a requisite precision. This process may be resolved into two distinct phases. One directed to the initial entry and the other directed to the long term maintenance.
For the long term maintenance, user terminals are provided with periodic time frames or slots to send an explicit synchronization burst to maintain this timing. These sync bursts are short, binary phase shift key (BPSK) sequences, with a fixed structure and convey no information other than the fact that the burst is present and whether the burst is early or late relative to the slot, as observed by the processing satellite. The user terminal sends these sync bursts in either the active or the standby state. In the long term maintenance phase, it is also assumed that the user terminal knows the range of a processing satellite with sufficient accuracy that its sync bursts will arrive at the processing satellite within a timing error that is a small fraction of the signaling epoch, which in no case should exceed approximately one third of the symbol epoch. The means by which the processing satellite learns of the sync burst slot or the initial entry which is reserved for its use, as well as how the user terminal learns the range to the processing satellite are set forth in detail in U.S. Ser. No. 09/270,167, filed on Mar. 16, 1999, and entitled xe2x80x9cInitial Entry Processor For A Processing Satellitexe2x80x9d and, TRW Docket No. 22-0056, filed herewith, and entitled xe2x80x9cSynchronization Scheme For A Processing Communication Satellitexe2x80x9d, which are each hereby incorporated by reference.
Each synchronization burst processor is generally required to serve the total bandwidth of a sub-band (typically 17 MHz), of which there are typically seven (7) sub-bands in each beam of the processing satellite coverage area. Transmission within each sub-band may be configured in one of three modes and the synchronization burst processor must be able to serve each such mode. These modes include type X where the sync burst processor handles one single high speed channel or user at a time with each user occupying a full bandwidth of the sub-band. Type Y where the sync burst processor handles typically five (5) medium size users or channels sharing the bandwidth by FDMA. Type Z where the synchronization burst processor concurrently receives signals from typically twenty five (25) low speed users or channels sharing the bandwidth again by FDMA.
Dedicated sync burst time slots within each frequency channel are provided in the uplink frequency and time plan of each sub-band for each beam of the processing satellite to accommodate sync bursts forwarded by user terminals. In time, these sync burst time slots are organized in sync burst blocks containing multiple time slots. Typically, there are twenty such slots in a block on one such channel per TDMA frame for mode z, 100 per frame per channel for mode Y, and 500 per frame for mode x. Each of these slots is sufficiently longer than the length N, of a sync burst (typically N=64 symbols) to avoid adverse interactions between consecutive sync bursts. A typical sync burst slot width is 72 symbols, thereby providing a guard band of 8 symbols. The product of the number of channels per sub-band and the number of slots per block is constant and is generally about 500 for the typical case. The duration of the sync burst block is also the same in each mode, which is about twenty-eight hundred and eighty microseconds (2880 xcexcs) for a typical case with the sync burst interval being concurrent across all channels (within a sub-band).
The synchronization burst processor is required to examine the signal presence within each sync burst slot and reach one of three decisions. These decisions include a sync burst is present within an acceptable timing error and it is either (1) early or (2) late, or (3) no sync burst is present within acceptable timing limits. The synchronization burst processor must also function reliably without knowing the phase of the uplink signal. However, the synchronization burst processor may rely on the signal amplitude being well controlled as a result of uplink power control procedures. The synchronization burst processor may also rely upon the incoming frequency of both the signal carrier and of the symbol epoch clock being very close to its own timing.
What is needed then is a synchronization burst processor for a processing satellite in a satellite based cellular communications system that meets the above requirements. This will, in turn, provide a synchronization burst processor for operation in a processing satellite that: is capable of operating solely on odd sample data; provides dual correlators; is capable of operating in multiple operating modes with different channelizations; does not respond to noise when synch bursts are absent; does not respond to poorly aligned sync bursts; reduces processing load due to operating on one sample per symbol (odd samples); reduces processing load due to efficient dual correlators; reduces data transferred within the satellite because of highly efficient report structures; and provides reprogrammable or loadable preamble sequence templates. It is, therefore, an object of the present invention to provide such a synchronization burst processor for a processing satellite operating in a satellite based cellular communications system.
In accordance with the teachings of the present invention, a synchronization burst processor for use in a processing satellite in a satellite based communications system is provided. The synchronization burst processor operates in multiple operating modes to perform double correlations and determine a modulus of these double correlations to determine if sync bursts are present and whether the sync bursts are early or late relative to a sync burst slot.
In one preferred embodiment, a synchronization burst processor for use in a processing satellite in a satellite based communications system includes a sync burst memory, a first double correlator, a second double correlator, and a modulus module. The sync burst memory is operable to store at least one sync burst transmitted from a terrestrial terminal to the processing satellite with the sync burst being formed from a quadrature pair sample set {p, q}. The first double correlator performs an early correlation and a late correlation of the p samples relative to a sync burst slot to generate an early correlation Pe and a late correlation Pl. The second double correlator performs an early correlation and a late correlation of the q samples relative to the sync burst slot to generate an early correlation Qe and a late correlation Ql. The modulus module determines an early modulus Re and a late modulus Rl from the early correlations Pe and Qe and from the late correlations Pl and Ql such that the early modulus Re and late modulus Rl are used to determine if the sync burst is present in the sync burst slot and if the sync burst is early or late relative to the sync burst slot.